葉文冠 主任

學歷

國立交通大學電子所 博士
國立成功大學微電子所 碩士
中原大學電子工程學系 學士

經歷

國家實驗研究院國家奈米元件實驗室 副主任
國立高雄大學工學院 院長
國立高雄大學通識中心 主任
國立高雄大學學務處 學務長
國立高雄大學電機系 系主任
聯華電子公司 (UMC) 研發部 (TD) 專案經理
台灣積體電路公司 tsmc 研發部 (TD) 研究生

研究與技術專長

VLSI Processes
Nano-scaled CMOSFETs
SOI MOSFET
FinFET

個人著作
  1. 碩士論文題目:選擇性鈦矽化合物在超大型積體電路上之運用 (Selective TiSix on VLSI Applications) (本論文與台灣積體電路公司(tsmc) R&D部門合作, 於tsmc完成)
  2. 博士論文題目:選擇性鎢沉積在極大型積體電路上之運用 (Selective CVD-W on ULSI Applications)(本論文為國科會與台灣積體電路公司(tsmc)產學合作計劃, 於國科會國家毫微米實驗室(NDL)完成)
  3. 葉文冠, ”半導體製程技術與元件設計” 東華書局出版, ISBN 978-957-483-510-2, 2008.
  4. 葉文冠, ”新世代積體電路製程技術〞, 東華書局出版,ISBN9789574836710, 2011.
  5. 葉文冠, ”積體電路製程技術與品質管理”, 東華書局出版,ISBN9789574836703 , 2011.
  6. 葉文冠, ”積體電路製程設計、佈局規劃及測試”, 東華書局,預計2014出版.

期刊論文
  1. Kwang-Jow Gan, Jeng-Jong Lu, Wen-Kuan Yeh, Yaw-Hwang Chen, Yan-Wun Chen, “Multiple-valued logic design based on the multiple-peak BiCMOSNDR Circuits”, International Journal of Engineering Science and Technology, pp. 1-6, 2016.
  2. Wen-Teng Chang, Member, IEEE, Li-Gong Cin, and Wen-Kuan Yeh, “Impact of Fin Width and Back Bias Under Hot Carrier Injection on Double-Gate FinFETs”, IEEE Transaction on Device and Materials Reliability, vol.12 , No.3 (2015), pp.1-4. (SCI)
  3. Min–Cheng Chen, Chih–Ming Wu, Yun–Fang Hou, Yi–Ju Chen, Chang–Hsien Lin, Chia–Yi Lin, Bo–Wei Wu, Wen–Kuan Yeh, “ A Si–based bulk FinFET by novel etching process with mask–less and photoresist–free lithography technique”, International Journal of Nanotechnology, Volume 12, pp.87-89,2015.(SCI)
  4. Wen-Kuan Yeh, Cheng-Li Lin, Tung-Huan Chou, Kehuey Wu, Jiann-Shiun Yuan,” The Impact of Junction Doping Distribution on Device Performance Variability and Reliability for Fully Depleted Silicon on Insulator with Thin BOX Layer MOSFETs “, IEEE Transactions on Nanotechnology, vol.14 Issue 2, pp.1536-1550. MARCH.(2015) .(SCI)
  5. Po-Ying Chen, Chi-Chang Chen, Wen-Kuan Yeh, Yukan Chang, Der-Chen Huang, Shyr-Shen Yu, Chwei-Shyong Tsai, Yu-Jung Huang, Wei-Cheng Lin, Shao-I Chu, Chung-Long Pan, Tsung-Hung Lin, and Shyh-Chang Liu, “Using Capacitance Sensor to Extract Characteristic Signals of Dozing from Skin Surface “, Journal of Sensors , October, 2014.
  6. Yi-Lin Yang, Tzu-Sung Yen, Jia-Jian Hong, Jie-Chen Wong, Chao-Chen Ku, Tai-Hsuan Wu, Tzuo-Li Wang, Chien-Yi Li, Bing-Tze Wu, Shih-Hung Lin, Wen-Kuan Yeh , “Examination of Hot-Carrier Stress Induced Degradation on Fin Field-Effect Transistor, Applied Physics Letter, L13-11687R 104(8):083505-083505-3 (2014) (Impact Factor: 3.79).
  7. Cheng-Li Lin, Po-Hsiu Hsiao, Wen-Kuan Yeh, Han-Wen Liu, Syuan-Ren Yang, Yu-Ting Chen, Kun-Ming Chen, and Wen-Shiang Liao, “Effects of Fin Width on Device Performance and Reliability of Double-Gate n-Type FinFETs, “IEEE Transactions on Electron Devices, Vol. 60, No. 11, pp.3639-3644 (2013). (2012 SCI Impact Factor =2.062, N/M= 18.1% (44/243) on categories: Engineering, Electrical and Electronic)
  8. Wen-Teng Chang, and Wen-Kuan Yeh, “Reliability of the Doping Concentration in an Ultra-thin Body and Buried Oxide Silicon on Insulator (SCI) and Comparison with a Partially Depleted SOI”, Microelectronics Reliability, vol 52, Nov (2013) pp..
  9. Jiann-Shiun Yuan, Cheng-Li Lin and Wen-Kuan Yeh, and C. Xiao, "Hot Electron Effect on FinFET RF Circuit Reliability" Advances in Microelectronic Engineering, Vol 52, Nov (2013) pp. 1-6.
  10. Jiann-Shiun Yuan, Hsu-Der Yen, Guo-Wei Huang, and Wen-Kuan Yeh, “Reliability Analysis of pHEMT Power Amplifier with an On-chip Linearizer" Microelectronics Reliability Vol 53, (2013) pp.1-6.
  11. Wen-Kuan Yeh , Po-Ying Chen, Kwang-Jow Gan, Jer-Chyi Wang, Chao Sung Lai, ”The impact of interface/border defect on performance and reliability of high-k/metal-gate CMOSFET”, Microelectronics Reliability, Vol 53, (2013) pp.265-269.
  12. Kwang-Jow Gan, Zheng-Jie Jiang, Cher-Shiung Tsai, Din-Yuen Chan, Jian-Syong Huang, Zhen-Kai Kao, and Wen-Kuan Yeh, “Design of NDR-Based Oscillators Suitable for the Nano-Based BiCMOS Technique”, Applied Mechanics and Materials, Vol. 328 (2013) pp . 669-673.
  13. J.S. Yuan, Hsuan-Der Yen ; Shuyu Chen, Ruey-Lue Wang, Guo-Wei Huang, Y.-Z. Juang, Chih-Ho Tu, Wen-Kuan Yeh, Jun Ma,” Experimental Verification of RF Stress Effect on Cascode Class-E PA Performance and Reliability”, IEEE Transaction on Device and Materials Reliability, vol.12 , No.3 (2012), pp.369-375.(SCI)
  14. H.D. Yen, J.S. Yuan, R.L. Wang, G.W. Huang, Wen-Kuan Yeh, F.S. Huang,” RF stress effects on CMOS LC-loaded VCO reliability evaluated by experiments., Microelectronics Reliability, Vol 52, Nov (2012) pp.2655-2659.
  15. Yi-Lin Yang, Wenqi Zhang, Chi-Yun Cheng, Yi-Ping Huang, Pin-Tseng Chen, Chia-Wei Hsu, Li-Kong Chin, Chien-Ting Lin, Che-Hua Hsu, Chien-Ming Lai, and Wen-Kuan Yeh, “Reliability Improvement of 28-nm High-k/Metal Gate-Last MOSFET Using Appropriate Oxygen Annealing,” IEEE ELECTRON DEVICE LETTERS, vol. 33, Aug, (2012) pp.1183-1185 (SCI)
  16. Yi-Lin Yang, Wenqi Zhang, Chi-Yun Cheng and Wen-kuan Yeh, “The Improvement of Reliability of High-k/Metal Gate pMOSFET Device with Various PMA Conditions," Active and Passive Electronic Components, (2012). (EI)
  17. Jiann-Shiun Yuan, Hsu-Der Yen, Guo-Wei Huang, Re-Lu Wang, and Wen-Kuan Yeh, RF Stress Effects on CMOS LC-Loaded VCO Reliability Evaluated by Experiments”, Microelectronics Reliability, JUNE, VOL. 12, NO. 2, (2012), pp. 369-374. (SCI)
  18. Jiann-Shiun Yuan, , Hsuan-Der Yen, Shuyu Chen, , IEEE, Ruey-Lue Wang, Guo-Wei Huang, Ying-Zong Juang, Chih-Ho Tu, Wen-Kuan Yeh, and Jun Ma, IEEE Transaction on Device and Materials Reliability, vol.58 , No.3 (2011), pp.369-375.(SCI)
  19. Wen-Kuan Yeh, Yu-Ting Chen, Fon-Shan Huang, Chia-Wei Hsu, Chun-Yu Chen, Yean-Kuen Fang, Kwang-Jow Gan, and Po-Ying Chen, “The Improvement of High-k/Metal Gate pMOSFET Performance and Reliability Using Optimized Si Cap/SiGe Channel Structure," IEEE Transaction on Device and Materials Reliability, vol.58 , No.3 (2011), pp.7-12.(SCI)
  20. Kwang-Jow Gan, Cher-Shiung Tsai, Chi-Wen Hsien, Yu-Kuang Li, and Wen-Kuan Yeh., “Design of monostable–bistable transition logic element using the BiCMOS-based negative differential resistance circuit”, Analog Integr Circ Sig Process (2011), pp. 379–385.
  21. Jiann-Shiun Yuan, Wen-Kuan Yeh, Shuyu Chen, Chia-Wei Hsu, “NBTI reliability on high-k metal-gate SiGe transistor and circuit performances", Microelectronics Reliability 51 (2011) 914–918.
  22. Wen-Teng Chang, Jian-An Lin, Chih-Chung Wang, and Wen-Kuan Yeh, “Effect of gate capping configurations and silicon-on-insulator thickness with external stresses on partially depleted metal-oxide-semiconductor field-effect transistors”, J. Vac. Sci. Technol. B 29, (2011) pp. 01A904 -01A907.
  23. Yu-Ting Chen, Kun-Ming Chen, Member, IEEE, Cheng-Li Lin, Wen-Kuan Yeh, Member, IEEE, Guo-Wei Huang, Member, IEEE, Chien-Ming Lai, Yi-Wen Chen, Che-Hua Hsu, and Fon-Shan Huang," Effect of NH3 Plasma Nitridation on Hot-Carrier Instability and Low-Frequency Noise in Gd-Doped High-κ Dielectric nMOSFETs," IEEE Transaction on ELECTRON DEVICE, vol.58 , No.3 . (2011), pp.812-818.(SCI)
  24. Yu-Ting Chen, K.-M. Chen, Wen-Kuan Yeh, C.-C. Wang,C-L. Lin, J.-S. Yuan, and F.-S. Yeh, ”Impact of SOI Thickness on FUSI-Gate CESL CMOS Performance and Reliability”, IEEE Transaction on Device and Materials Reliability, vol. (2011) pp.41-48, (SCI)
  25. Po-Ying Chen, Ming-Hsing Tsai, Wen-Kuan Yeh, Ming-Haw Jing, and Yukon Chang “Reliability between wafer fracture reduction and controlling during the edge manufacturing process ” Microelectronic Engineering, vol. 87 (2010) pp. 1809-1815.
  26. Po-Ying Chen, Ming-Hsing Tsai, Wen-Kuan Yeh, Ming-Haw Jing, and Yukon Chang “ Relationship between wafer edge design and its ultimate mechanical strength, Microelectronic Engineering, vol. 87 (2010) pp.2065-2070 (SCI)
  27. Kwang-Jow Gan, Cher-Shiung Tsai, Yan-Wun Chen, Wen-Kuan Yeh, Voltage-Controlled Multiple-Valued Logic Design Using Negative Differential Resistance Devices, Solid State Electronics, vol 54. (2010) pp.1637-1640, (SCI)
  28. Wen-Teng Chang, Chih-Chung Wang, jian-An Lin, and Wen-Kuan Yeh, ”External Stresses on Tensile and Compressive Contact Etching Stop Layer SOI MOSFETs”, IEEE Transaction on ELECTRON DEVICE, vol.57 , No8. (2010), pp. 1889-1894. (SCI)
  29. Po-Ying Chen, Ming-Hsing Tsai, Wen-Kuan Yeh, Ming-Haw Jing, and Yukon Chang “Relationship between wafer edge design and its ultimate mechanical strength” Microelectronic Engineering, vol. 87 (2010) pp.2065-2070 (SCI)
  30. J.S. Yuan, J. Ma, C.W. Hsu, and Wen-Kuan Yeh, “Impact of Strain on Hot Electron Reliability of Dual-Band Power Amplifier and Integrated LNA-Mixer RF Performances”, Microelectronics Reliability, vol. 50 (2010) pp. 807-812.
  31. Chia-Wei Hsu, Yean-Kuen Fang, Wen-Kuan Yeh, Chun-Yu Chen, Yen-Ting Chiang , Feng-Renn Juang, Chien-Ting Lin, Chien-Ming Lai, “ Improvement of TDDB reliability, characteristics of HfO2 high-k/metal gate MOSFET device with oxygen post deposition annealing”, Microelectronics Reliability, (2010) pp.110-115.
  32. Cheng-Li Lin, Yu-Ting Chen, Fon-Shan Huang, Wen-Kuan Yeh, and Chien-Ting Lin, “The Impact of Oxide Traps Induced by SOI Thickness on Reliability of Fully Silicide Metal-Gate Strained SOI MOSFET”, IEEE ELECTRON DEVICE LETTERS, vol. 31, Feb, (2010) pp.165-167 (SCI)
  33. Chia-Wei Hsu, Yean-Kuen Fang, Wen-Kuan Yeh, Chun-Yu Chen, Chien-Ting Lin, Che-Hua Hsu, Li-Wei Cheng, and Chien-Ming Lai,” Effect of Nitrogen Incorporation in a Gd Cap Layer on the Reliability of Deep-Submicrometer Hf-Based High-k/Metal-Gate nMOSFETs, IEEE ELECTRON DEVICE LETTERS, vol. 30, July, (2009) pp.781-783 (SCI)
  34. Po-Ying Chen, Ming-Hsing Tsai, Wen-Kuan Yeh, Ming-Haw Jing, and Yukon Chang,” Investigation of the Relationship between Whole-Wafer Strength and Control of its Edge Engineering”, Vol. , Japanese Journal of Applied Physics , No.48 , (2009) pp.819-823. (SCI)
  35. Wen-Kuan Yeh, Jean-An Wang, Ming-Hsing Tsai, and Chien-Ting Lin, “The Impact of Strain Technology on FUSI Gate SOI CMOSFET”, IEEE Transaction on Device and Materials Reliability, vol. 9 (2009) pp.77-79, (SCI)
  36. Chia-Wei Hsu, Yean-Kuen Fang, Chien-Ting Lin, Wen-Kuan Yeh, Che-Hua Hsu ,Chieh-Ming Lai b, Li-Wei Cheng, Mike Ma, “Significant improvement of 45 nm and beyond complementary metal oxide semiconductor field effect transistor performance with fully silicided and ultimate spacer process technology”, Thin Solid Films vol. 516 (2008) pp. 7741–7743.
  37. Chia-Wei Hsu, Yean-Kuen Fang, Wen-Kuan Yeh, Chien-Ting Lin , “Significantly improving sub-90 nm CMOSFET performances with notch-gate enhanced high tensile-stress contact etch stop layer”, Microelectronics Reliability, 48 (2008) pp. 1791–1794.
  38. Shuo-Mao Chen , Yean-Kuen Fang , Wen-Kuan Yeh , I.C. Lee , Yen-Ting Chiang , “A high current gain gate-controlled lateral bipolar junction transistor with 90 nm CMOS technology for future RF SoC applications”, Solid-State Electronic, 52 (2008), pp.1140-1144
  39. Po-Ying Chen, Shen-Li CHEN, Ming-Hsing TSAI, Wen-Kuan YEH, and Yu Kuan CHANG, “Elucidating the Effects of Current Stress History on Reliability Characteristics by Dynamic Analysis” Vol. 47, Japanese Journal of Applied Physics , No. 10, (2008) pp. (SCI)
  40. Po-Ying Chen, Heng-yu Kung, Yi-Shao Lai, Ming Hsiung Tsai, and Wen-Kuan Yeh, “Reliability and Characteristics of Wafer-Level Chip Scale Packages under Current stress” Japanese Journal of Applied Physics Vol. 47, No. 2, (2008) pp.1053-1057. (SCI)
  41. Chien-Ting Lin, Yean-Kuen Fang, Wen-Kuan Yeh, Chieh-Ming Lai, Che-Hua Hsu, Li-Wei Cheng, and Guang Hwa Ma.,”Impacts of Notched-Gate Structure on Contact Etch Stop ayer (CESL)Stressed 90-nm nMOSFET”, IEEE ELECTRON DEVICE LETTERS, vol. 28, May, (2007) pp.376-377. (SCI)
  42. Wen-Kuan Yeh, “The Impact of Mobility Enhanced Technology on Device Performance and Reliability for sub-90nm SOI nMOSFETs, Microelectronic Engineering, no. 84, pp. 2077-2080 (2007).
  43. Chien-Ting Lin, Yean-Kuen Fang, Chieh-Ming Lai, Wen-Kuan Yeh, Che-Hua Hsu, Li-Wei Cheng, Yao-Tsung Huang, and Guang Hwa Ma. “Extra Bonus on Transistor Optimization with Stress Enhanced Notch-gate Technology for sub-90nm CMOSFET” Japanese Journal of Applied Physics Vol. 46, No. 4B, (2007) pp.2131-2133. (SCI)
  44. Chieh-Ming Lai, Yean-Kuen Fang, Chien-Ting Lin, Wen-Kuan Yeh, “Efficient Mobility Enhancement Engineering on 65nm Fully Silicide complementary MOSFET Using Second Contact Etch Stop Layer Process, ” Japanese Journal of Applied Physics Vol. 46, No. 4B, (2007) pp.2127-2130. (SCI)
  45. Chien-Ting Lin, Yean-Kuen Fang, Wen-Kuan Yeh, Tung-Hsing Lee, Ming-Shing Chen, Chieh-Ming Lai, Che-Hua Hsu, Liang-Wei Chen, Li-Wei Cheng, and Mike Ma,, “A Novel Strain Method for Enhancement of 90-nm Node and Beyond FUSI-Gated CMOS Performance”, IEEE ELECTRON DEVICE LETTERS, vol. 28, FEB, (2007) pp.111-113. (SCI)
  46. Chieh-Ming Lai, Yean-Kuen Fang, Wen-Kuan Yeh, Chien-Ting Lin, and T. H. Chou, “The Investigation of Post-Annealing-Induced Defects Behavior on 90-nm In Halo nMOSFETs With Low-Frequency Noise and Charge-Pumping Measuring”, IEEE ELECTRON DEVICE LETTERS, vol. 28, FEB, (2007) pp.142-144. (SCI)
  47. Chien-Ting Lin, Yean-Kuen Fang, Wen-Kuan Yeh, Tung-Hsing Lee, Ming-Shing Chen, Che-Hua Hsu, Liang-Wei Chen, Li-Wei Cheng, and Mike Ma, “Effect of Silicon Thickness on Contact-Etch-Stop-Layer-Induced Silicon/Buried-Oxide Interface Stress for Partially Depleted SOI ” IEEE ELECTRON DEVICE LETTERS, vol.27 , No12. (2006), pp. 963-965. (SCI)
  48. Chieh-Ming Lai, Yean-Kuen Fang, Chien-Ting Lin, and Wen-Kuan Yeh " The Geometry Effect of Contact Etch Stop Layer Impact on Device Performance and Reliability for 90-nm SOI nMOSFETs, IEEE Transaction on ELECTRON DEVICE, vol.53 , No11. (2006), pp. 2779-2785. (SCI)
  49. Chieh-Ming Lai, Yean-Kuen Fang, Wen-Kuan Yeh, S. H. Chen, and Ta-Hsun Yeh “Stress Technology Impact on Device Performance and Reliability for <100> sub-90nm SOI CMOSFETs” Japanese Journal of Applied Physics Vol. 45, No. 4B, (2006) pp.3053-3057. (SCI)
  50. Chien-Ting Lin, Yean-Kuen Fang, Wen-Kuan Yeh, H. C. Chang, C. H. Hsu, L. W. Chen, M. L. Lee, C. T. Tsai, and W.T. Shiau “Investigation and Modeling of Stress Interactions on 90 nm SOI CMOS with Various Mobility Enhancement Approaches” Japanese Journal of Applied Physics Vol. 45, No. 4B, (2006) pp.3049-3052. (SCI)
  51. Mao-Chyuan Tang, Yean-Kuen Fang, Wen-Kuan Yeh, S. H. Chen, and Ta-Hsun Yeh “Systematic Analysis and Modeling of On-Chip Spiral Inductors for CMOS RFIC Application” Japanese Journal of Applied Physics Vol. 45, No. 4B, (2006) pp.3247-3250. (SCI)
  52. Wen-Kuan Yeh, Chao-Ching Ku*, Shuo-Mao Chen*, Yean-Kuen Fang*, and C. P. Chao, "Effect of Extrinsic Impedance and Parasitic Capacitance on Figure of Merit of RF MOSFET," IEEE Transaction on ELECTRON DEVICE, vol. 52, No.9. (2005), pp. 2054-2060 (SCI)
  53. Chieh-Ming Lai, Yean-Kuen Fang, Shing-Tai Pan, Wen-Kuan Yeh, “Width Effect on Hot-Carrier-Induced Degradation for 90nm Partially Depleted SOI CMOSFETs” Japanese Journal of Applied Physics Vol. 44, No. 4B, 2005, (SCI)
  54. Kun-Ming Chen, Hsin-Hui Hu, Guo-Wei Huang, Wen-Kuan Yeh, and Chun-Yen Chang, " Low-Frequency Noise in Partially Depleted SOI MOSFETs operating from Linear Region to saturation Region at Various Temperatures," Japn. J. of Applied Physics, vol. 43, No. 4B (2004) pp.2188-2189. (SCI)
  55. Wen-Kuan Yeh, Shuo-Mao Chen, and Yean-Kuen Fang, “Substrate Noise Coupling Characterization and Efficient Suppression in CMOS Technology”, IEEE ELECTRON DEVICE LETTERS, vol. 51, May, (2004) pp.817-819. (SCI)
  56. Wen-Kuan Yeh, and Jung-Chun Lin, “Efficient Improvement of Hot Carrier-Induced Degradation for 0.1um Indium-halo nMOSFET”, IEEE ELECTRON DEVICE LETTERS, vol. 50, April, (2004) pp.642-643. (SCI)
  57. Wen-Kuan Yeh, Yean-Kuen Fang, and Mao-Chieh Chen, “ The Effect of Thermal Treatment on Device characteristic and reliability for Sub-100nm CMOSFET”, IEEE Transaction on Device and Materials Reliability, vol 51. (2004) pp.256-262. (SCI)
  58. Wen-Kuan Yeh, Sho-Mao Chen, “Efficient Suppression of Substrate Noise Coupling in Complementary Metal-Oxide-Semiconductor Field-Effect-Transistor”, Japn. J. of Applied Physics, vol. 43, No. 4B (2004) pp.1695-1698. (SCI)
  59. Jung-Chun Lin, Wen-Kuan Yeh, Tan-Fu Lei, “Efficient Improvement of Hot-Carrier-Induced Device's Degradation for Sub-0.1um Complementary Metal-Oxide-Semiconductor Field-Effect-Transistor,” Japn. J. of Applied Physics, vol. 43, No. 4B (2004) pp.1737-1741. (SCI)
  60. Ming-Chun Hsieh, Yean-Kuen Fang, Chun-Hui Chen, Shuo-Mao Chen and Wen-Kuan Yeh, "Design and Fabrication of deep Submicron CMOS Technology Compatible Suspended High-Q Spiral Inductor," IEEE Transaction on ELECTRON DEVICE, vol.51. (2004), pp.324-331. (SCI)
  61. Kun-Ming Chen, Guo-Wei Huang, Sheng-Chun Wang, Wen-Kuan Yeh, Yean-Kuen Fang, and Fu-Liang Yang, "Characterization and Modeling of SOI Varactors at Various Temperatures," IEEE Transaction on ELECTRON DEVICE, vol.51. (2004), pp.427-433. (SCI)
  62. Wen-Kuan Yeh, Wen-Hang Wang, Yean-Kuen Fang, and Fu-Liang Yang, “0.1um Partially Depleted SOI CMOSFET Hot-Carrier-induced Degradation ” Japn. J. of Applied Physics, vol. 42, No. 4B (2003), pp. 1993-1998.
  63. Wen-Kuan Yeh, Wen-Hang Wang, Yean-Kuen Fang, Mao-Chieh Chen and Fu-Liang Yang, “Hot-Carrier-Induced Degradation for Partially Depleted SOI 0.25-0.1um CMOSFET with 2nm Thin Gate Oxide”, IEEE Transaction on ELECTRON DEVICE, vol.49. (2002), pp.2157-2162.
  64. Wen-Kuan Yeh and Jih-Wen Chou, “The Impact of Gate Oxide Scaling (3.2-1.2nm) for Sub-100nm CMOSFETs” Thin Solid Film, 419(2002), pp.218-223.
  65. Wen-Kuan Yeh, Wen-Hang Wang , Yean-Kuen Fang, and Fu-Liang Yang, “Temperature dependence of Hot-Carrier-Induced Degradation in 0.1um SOI nMOSFETs with thin oxide”, IEEE ELECTRON DEVICE LETTERS, vol. 23 (2002), pp.425-427.
  66. Wen-Kuan Yeh, Wen-hang, Yean-Kuen Fang, and Fu-Liang Yang,” New Observations on Hot-Carrier Degradation in 0.1um SOI nMOSFETs”, Japn. J. of Applied Physics Letter, No41, 2002, ppL01-L03.
  67. Wen-Kuan Yeh and C-T. Huang, “Thermal Effect of 0.1um Partially Depleted SOI CMOSFET” Microelectronic Engineering, vol.59 (2001), pp.475-482.
  68. Wen-Kuan Yeh and Jih-Wen Chou, “Optimum Treatment for improvement of Indium-halo structure for sub-0.1um n-type Metal-Oxide-Semiconductor Transistor”, Japn. J. of Applied Physics Letter, No11 (2001), pp1139-1141.
  69. Wen-Kuan Yeh and Jih-Wen Chou, “Optimum Halo Structure for Sub-0.1m CMOSFETs” IEEE Transcation on ELECTRON DEVICE, vol. 48 (2001), pp.2357-2362.
  70. Wen-Kuan Yeh and Jih-Wen Chou, “Temperature dependency of 0.1m Partially Depleted SOI CMOSFET” IEEE ELECTRON DEVICE LETTERS, vol. 22 (2001), p. 339-341.
  71. Coming Chen, Sun-Jay Chang, Wen-Kuan Yeh, “The Effects of Super-Steep-Retrograde Indium Channel Profile on Deep Submicron n-Channel Metal-Oxide-Semiconductor Field-Effect Transistor”, Japn. J. of Applied Physics, vol38 (2001), pp.75-79.
  72. Sun-Jay Chang, Wen-Kuan Yeh and Shin-Wei Sun, “A novel Sacrificial Gate Stack process for Suppression of Boron Penetration in P-MOSFET with Shallow BF2-Implanted Source/Drain Extension” IEEE ELECTRON DEVICE LETTERS, vol. 21 (2000), p1-3.
  73. Wen-Kuan Yeh Jih-Wen Chou, and Shin-Wei Sun, "A Low Thermal-Budget high-performanced 0.25-0.18um merged logic and DRAM” Japn. J. of Applied Physics, vol38 (2000), p2162-2165.
  74. Wen-Kuan Yeh and Shin-Wei Sun,"A Novel Shallow Trench Isolation with Mini-Spacer Technology” Japn. J. of Applied Physics, vol38 (1999), p2300-2305.
  75. Wen-Kuan Yeh and Mao-Chieh Chen,"A new tungsten gate MOS using CVD process ", J. Electrochem. Soc., 1997. p. 214-217. @ note:This paper has been filed to patents of Taiwan and USA ;註:本篇已經獲得中華民國與美國專利。
  76. Wen-Kuan Yeh et al, "Disordered Si/SiGe superlattices grown by ultrahigh vacuum CVD" Applied Surface Science, 1996.
  77. Wen-Kuan Yeh et al, "Uniformity of Epilayer grown by ultrahigh-vacuum CVD" Materials Chemistry and Physics, 1996.
  78. Wen-Kuan Yeh and Mao-Chieh Chen,"Thermal Stability of W-contacted Junction Diodes ", J. Electrochem. Soc., 1996. p. 2053-2059. (NSC84-2622-E009-007-1)
  79. Wen-Kuan Yeh and Mao-Chieh Chen,"The effect of surface pretreatment of submicron contact hole on selective tungsten chemical vapor deposition" Journal Vacuum Society Technology, 1996, p. 167-173. (NSC84-2622-E009-007-1)
  80. Wen-Kuan Yeh and Mao-Chieh Chen,"Deposition properties of selective W-CVD ", Journal Material Chemical Physics, 1996, p. 284-287.
  81. Wen-Kuan Yeh and Mao-Chieh Chen,"An Efficient Improvement on Thermal Stability of W-filled Contact", Japn. J. of Applied Physics, 1996. p.1115-1119. (NSC84-2622-E009-007-1)
  82. Wen-Kuan Yeh and Mao-Chieh Chen,"An Efficient Preclean for Selective CVD-W of Submicron W plug on Al", J. Electrochem. Soc., 1995, p. 3584-3588. (NSC84-2622-E009-007-1);@ note1:this paper has been quoted by "Contamination News", Journal of Semiconductor International (October, 1995). 註1:本篇曾經被引用在 "Contamination News", Journal of Semiconductor International (October, 1995). @ note2:This paper has been filed to patents of Taiwan and USA 註2:本篇已經獲得中華民國與美國專利。
  83. Wen-Kuan Yeh, Mao-Chieh Chen, and Mao-Shiung Lin,"Thermal Stability of AlSiCu/W/n+p Diodes with or without TiN layer" Thin Solid Film, 1995, p. 526-530. (NSC84-2622-E009-007-1)
  84. Wen-Kuan Yeh, Mao-Chieh Chen, and Mao-Shiung Lin, "Selective Tungsten CVD on Submicron Contact Hole" Thin Solid Film, 1995, p. 462-466.

會議論文
  1. Yao-Jen Lee, Fu-Ju Hou, Shang-Shiun Chuang, Fu-Kuo Hsueh, Kuo-Hsing Kao, Po-Jung Sung, Wei-You Yuan, Jay-Yi Yao, Yu-Chi Lu, Kun-Lin Lin, Chien-Ting Wu, Hisu-Chih Chen, Bo-Yuan Chen, Guo-Wei Huang, Henry J. H. Chen, Jiun-Yun Li, Yiming Li, Seiji Samukawa, Tien-Sheng Chao, Tseung-Yuen Tseng, Wen-Fa Wu, Tuo-Hung Hou, and Wen-Kuan Yeh, “Diamond-shaped Ge and Ge0.9Si0.1 Gate-All-Around Nanowire FETs with Four {111} Facets by Dry Etch Technology”, IEEE International Electron Devices Meeting, USA, 2015.
  2. Yao-Jen Lee, Ta-Chun Cho, Po-Jung Sung, Kuo-Hsing Kao, Fu-Kuo Hsueh , Fu-Ju Hou, Po-Cheng Chen, Hsiu-Chih Chen, Chien-Ting Wu, Shu-Han Hsu, Yi-Ju Chen, Yao-Ming Huang, Yun-Fang Hou, Wen-Hsien Huang, Chih-Chao Yang, Bo-Yuan Chen, Kun-Lin Lin, Min-Cheng Chen, Chang-Hong Shen, Guo-Wei Huang, Kun-Ping Huang, Michael I. Current, Yiming Li, Seiji Samukawa, Wen-Fa Wu, Jia-Min Shieh, Tien-Sheng Chao, Wen-Kuan Yeh, “High Performance Poly Si Junctionless Transistors with Sub-5nm Conformally Doped Layers by Molecular Monolayer Doping and Microwave Incorporating CO2 Laser Annealing for 3D Stacked ICs Applications”, IEEE International Electron Devices Meeting, USA, 2015.
  3. Chih-Chao Yang, Jia-Min Shieh, Tung-Ying Hsieh, Wen-Hsien Huang, Hsing-Hsiang Wang, Chang-Hong Shen, Tsung-Ta Wu, Yun-Fang Hou, Yi-Ju Chen, Yao-Jen Lee, Min-Cheng Chen, Fu-Liang Yang, Yu-Hsiu Chen, Meng-Chyi Wu, and Wen-Kuan Yeh, “Enabling Low Power BEOL Compatible monolithic 3D+nanoelectronicsfor IoTs Using Local and Selective Far-Infrared Ray Laser Anneal Technology:, IEEE International Electron Devices Meeting, USA, 2015.
  4. M.-C. Chen, K.-H. Li, L.-J. Li, M.-Y. Li, Y.-H. Chang, C.-H. Lin, Y.-J. Chen, Y.-F. Hou, C.-C. Chen, B.-W. Wu, C.-S. Wu, I. Yang, Y.-J. Lee, J.-M. Shieh, W.-K. Yeh, P.-C. Su, T. Wang, F.-L. Yang, and C. Hu, “TMD FinFET with 4 nm Thin Body and Back Gate Control for Future Low Power Technology”, IEEE International Electron Devices Meeting, USA, 2015.
  5. K. S. Li, P.-G. Chen, D. Y. Lai, C. H. Lin, C.-C. Cheng, C. C. Chen, M.-H. Liao, M. H. Lee, M. C. Chen, J. M. Sheih, W. K. Yeh, F. L. Yang , “Sub-60mV-Swing Negative-Capacitance FinFET without Hysteresis”, IEEE International Electron Devices Meeting, USA, 2015.
  6. T.-T. Wu, C.-H. Shen, J.-M. Shieh, W.-H. Huang, H.-H. Wang, F.-K. Hsueh, H.-C. Chen, C.-C. Yang, T.-Y. Hsieh, B.-Y. Chen, Y.-S. Shiao, C.-S. Yang, G.-W. Huang, K.-S. Li, T.-J. Hsueh, C.-F. Chen, W.-H. Chen, M.-F. Chang, W.-K. Yeh, “Low-Cost and TSV-free Monolithic 3D-IC with Heterogeneous Integration of Logic, Memory and Sensor Analogy Circuitry for Internet of Things”, IEEE International Electron Devices Meeting, USA, 2015.
  7. Wen-Kuan Yeh, Wenqi Zhang and Yi-Lin Yang “The Study onWidth Quantization impact on Device Performance and Reliability for high-k/metal Tri- Gate FinFET”, IEEE Proceedings of EDSSC, Singapore, 2015.
  8. Y.-J. Lee, T.-C. Cho, K.-H. Kao,P.-J. Sung1, P.-C. Huang, F.-K. Hsueh, C.-T. Wu, S.-H. Hsu, W. -H. Huang, Yiming Li, Michael I. Current, B. Hengstebeck, J. Marino, J.-M. Shieh, T.-S. Chao, W. -K. Yeh, “A Novel Junctionless FinFET Structure with Sub-5nm Shell Doping Profile by Molecular Monolayer Doping and Microwave Annealing”, IEEE International Electron Devices Meeting, USA, 2014.
  9. Min-Cheng Chen, Chia-Yi Lin, Kai-Hsin Li, Lain-Jong Li, Chang-Hsiao Chen, Cheng-Hao Chuang, Ming-Dao Lee, Yi-Ju Chen, Yun-Fang Hou, Chang-Hsien Lin, Chun-Chi Chen, Bo-Wei Wu, Cheng-San Wu, Ivy Yang, Yao-Jen Lee, Wen-Kuan Yeh, Tahui Wang, Fu-Liang Yang , “Hybrid Si/2D Electronic Double Channels Fabricated Using Solid Few-Layer-MoS2 Stacking for Vth Matching and CMOS-Compatible 3DFETs “, IEEE International Electron Devices Meeting, USA, 2014.
  10. (Best paper最佳論文獎) Wen-Kuan Yeh, Wen-Teng Chang, Po-Ying Chen and Cheng-Li Lin, “Junction induced Variation and Reliability for Ultra-Thin-Body and Bulk Oxide CMOSFETs”, Proceedings of IPFA, Singapore (2014).
  11. Wen-Kuan Yeh, Chun-Ming Lai, Li-Kong Chin, and Po-Ying Chen “Device Variability and Reliability Check for Ultra-Thin-Body and Bulk Oxide CMOSFETs”, IEEE Proceedings of EDSSC, HongKong, China, (2013).
  12. Cheng-Li Lin, Chun-Hung Soh, Wen-Kuan Yeh, Chien-Ting Lin, Chun-Ming Wu, Yao-Hsiang Yang, Wei-Yi Chang, and Yen-Lun Huang, “Comprehensive Device Reliability and Oxide Traps Distribution Analysis by the Low Frequency Noise in Ultra-Thin Body SOI (UTBSOI) MOSFETs,” Int. Nanotechnology Materials and Devices Conference (NMDC), MP-4-11 (Oral), Oct. 06-09, National Cheng Kung University, Tainan, Taiwan, 2013.
  13. Chun-Hung Soh, Cheng-Li Lin, Wen-Kuan Yeh, and Chien-Ting Lin, “Electrical Characteristics of Different Pocket Implantation and the Body Charge Accumulation Effects of Ultra-Thin Body SOI MOSFET,” 2013 6th Electronic Technology Symposium (2013 ETS), May 24, I-Shou University, Kaohsiung, Taiwan, BP-13, p.14, 2013.
  14. Kwang-Jow Gan, Zheng-Jie Jiang, Din-Yuen Chan, Cher-Shiung Tsai, Jian-Syong Huang, Zhen-Kai Kao, and Wen-Kuan Yeh, "Design and Application of Van Der Pol Oscillator Using NDR Circuit", IEEE 2nd International Symposium on Next-Generation Electronics (ISNE), I-Shou University, Kaohsiung, Taiwan, Feb. 25-26, (2013) pp 329-332
  15. (最佳論文獎)Wenqi Zhang, Jhe-Hao Chang, Yen-Hsin Chen, Yi-Lin Yang, Chun-Ming Lai, Shi-Hao Wang, Li-Kong Chin and Wen-Kuan Yeh, ”Impact of Doping Concentration on Device Characteristic and Reliability in Ultra-Thin-Body and BOX (UTBB) MOSFETs”, Proceedings of IEDMS, Kaohsiung, Taiwan, 2012.
  16. (invited Talk) Wen-Kuan Yeh, “A Advanced Strain Channel Technology for Ultra Thin Body and Bulk Oxide SOI CMOSFET ”, WIMNACT2012, Nov, 28, 2012, Xidan University, Xian, China.
  17. (invited Talk) Wen-Kuan Yeh, P. Y. Chen, Y. L Yang, “A Proposed High Manufacturability Strain Technology for High-k/Metal Gate SiGe channel UTBB CMOSFET ”, ICSICTS, Nov, 2012, Xian, China.
  18. C. W. Chen, C. L. Lin and W. K. Yeh, “Characterization and Improvement of Charge Trapping in Gd Incoporatrated Hf based high-k/Metal gated nMOSFET, SSDM, Oct. 7-9, Sendi, Japan, 2012.
  19. W.K. Yeh, C. Y. Cheng, Y. L Yang, C.T. Lin , C.M. Lai, Y.W.Chen, C. H. Hsu, C. W. Yang, and P. Y. Chen, “A Proposed High Manufacturability Strain Technology for High-k/Metal Gate SiGe-SOI CMOSFET ”, SOI Conference, October, Tempe, Arizoa, USA, 2011.
  20. T-H Lee, S-M Chen, C-W Hsu, Y-K Fang, F-R-Juang, W-K Yeh, “Capping Layer Induced Degradation in Nano MOSFET with Scaled IL”, IEEE International Nano Electronics Conference (INEC), Taoyuan, Taiwan, June 21-24, 2011.
  21. K. J. Gan, C. H. Chang, J. J. Lu, C. L. Lin, Y. K. Su, B. J. Li, and W. K. Yeh, “Growth of Carbon Nanotube Using Microwave Plasma Chemical Vapor Deposition and Its Application to Thermal Dissipation of High-Brightness Light Emitting Diode”, International Conference of Electrical and Electronics Engineering, pp. 1439-1443, July 6-8, 2011, London, U.K.
  22. (invited Talk) Wen-Kuan Yeh, Jean-An Wang , Chien-Ting Lin, Li-Wei Cheng, Mike Ma, “A Proposed High Performance High-k/Metal Gate CMOSFET Process with Optimism Strained Si cap/SiGe p-channel and Relaxed SiGe n-channel”, ICSICTS, Nov, 2010, Shanghai, China.
  23. Kwang-Jow Gan, Ping-Feng Wu, Wu-Yan, Shie Cher-Shiung Tsai, Dong-Shong Liang, Cheng-Hsiung Tsai, and Wen-Kuan Yeh, “Frequency Multiplier Design Using BiCMOS-Based Multiple-Peak NDR Circuit”, IEEE Proceedings of EDSSC, HongKong, China, 2010.
  24. W. K. Yeh, C. W. Hsu, Y. K. Fang, C. Y. Chen, C. T. Lin, P. Y. Chen, “Characterization the Random Telegraph Noise in High-k/Metal gate device for 32nm nMOSFETs and pMOSFET”, Solid-State Device and Materials, September, Tokyo, Japan, 2010.
  25. C. W. Hsu, Y. K. Fang, C. Y. Chen, W. K. Yeh, C. T. Lin, P. Y. Chen, “High-k/metal Gate pMOSFET performances and reliability with Optimism Si Cap/SiGe channel structure”, Solid-State Device and Materials, September, Tokyo, Japan, 2010.
  26. (invited Talk) W. K. Yeh, C. C. Wang, C.W. Hsu, Y.K. Fang, S. M. Wu, C. C. Ou, C. L. Lin, K. J. Gan, C. J. Weng, P. Y. Chen, J. S. Yuan, J. J. Liou “Impact of Oxide Trap Charge on Performance of Strained Fully Depleted SOI Metal-Gate MOSFET” IEEE Proceedings of EDSSC, Xian, China, 2009.
  27. Chia-Wei Hsu, Wen-Kuan Yeh, “Strain Technology on Device Reliability for SOI CMOSFET”, IEEE Proceedings of IEDMS, Taoyuan, Taiwan, 2009.
  28. “Ruey-Lue Wang; Hsuan-Der Yen; Wen-Kuan Yeh; Yi-Jiue Shie”, A 1.2V low-power CMOS voltage-controlled oscillator (VCO) using current-reused configuration with balanced resistors for IEEE 802.16e”, ICSICTS, Nov, 2008, Bejing, China.
  29. Wen-Kuan Yeh; Jean-An Wang; Chien-Ting Lin; Li-Wei Cheng; Mike Ma; The impact of stain technology on FUSI gate SOI CMOSFET and device performance enhancement for 45nm node and beyond”, ICSICTS, Nov, 2008, Bejing, China.
  30. Po-Ying Chen Chwei-Shyong Tsai Ming-Hsiung Tsai Heng-Yu Kung Shen-Li Chen Jing, M.H. Wen-Kuan Yeh Dynamic scanning method to clarify the mechanism of WLCSP package reliability issue”, ICSICTS, Nov, 2008, Bejing, China.
  31. Po-Ying Chen; Chen, S.L.; Tsai, M.H.; Jing, M.H.; Lin, T.-C.; Wen-Kuan Yeh’” Effect of crystal-originated particles (COPs) on ULSI process integrity “, ICSICTS, Nov, 2008, Bejing, China.
  32. Wen-Teng Chang; Jian-An Lin; Wen-Kuan Yeh,”Piezoresistive sensor of short- and long- channel MOSFETs on (100) silicon”, ICSICTS, Nov, 2008, Bejing, China.
  33. Sung-Mao Wu; Wang-Yu Lin; Kao-Yi Wang; Chien-Hsiang Huang; Wen-Kuan Yeh, “The high balance symmetric balun for WLAN and WiMAX application using the Integrated Passive Device (IPD) technology”, ICSICTS, Nov, 2008, Bejing, China.
  34. (invited Talk) Wen-Kuan Yeh, Jean-An Wang , Chien-Ting Lin, “The Impact of Strain Technology on Device Characteristic and Reliability for FUSI Gate SOI CMOSFET”, IEDMS, Nov, 2008, Taiwan.
  35. C. W. Hsu, Y. K. Fang, W. K. Yeh, J. Y. Chen, C. T. Lin , “Improving Hf-based High-k/Metal-gate nMOSFET Performance with with Gadolinium Cap Layer”, Solid-State Device and Materials, September, Tokyo, Japan, Sept. 21-24, 2008.
  36. W.T. Chang, J.A. Lin, Y.C. Huang, Y.S. Ju and W.K. Yeh, “Piezoresistive Coefficients of <110> MOSFETs Using External Force”, IWNE, Nov, 2008, Taiwan.
  37. (invited Talk) Wen-Kuan Yeh, Jean-An Wang , Chien-Ting Lin, Li-Wei Cheng, Mike Ma, “The Impact of Strain Technology on Device Characteristic and Reliability for FUSI Gate SOI CMOSFET and Device Performance Enhancement for 45nm node”, ICSICTS, Oct, 2008, Beijing, China.
  38. Chun-Jen Weng ,Wen-Kuan Yeh, Chia-Chih Ou,”METROLOGY OF SEMICONDUCTOR BEOL NANOTECHNOLOGY LITHOGRAPHY AND GAP FILL PROCESSES INTEGRATION”, ISTC, March, 2008, Shanghai, China.
  39. (invited talk) W.-K. Yeh, C.-W. Hsu, C.-M. Lai, C.-T. Lin, Y.-K. Fang, C.-H. Hsu, L.-W. Chen, Y.-T. Huang3, C.-T. Tsai, “ Efficient Transistor Optimization with Stress Enhanced Notch-gate Technology for sub-90nm CMOSFET, IEEE Proceedings of EDSSC, Tainan, Taiwan, 2007.
  40. Jiun-Yu Chen, Jean-An Wang, Wen-Kuan Yeh , The Impact of Strain Technology on Device Performance and Reliability for sub-90nm FUSI SOI MOSFETs, IEEE Proceedings of EDSSC, Tainan, Taiwan, 2007.
  41. Chia-Wei Hsu, Wen-Kuan Yeh, Chieh-Ming Lai, Chien-Ting Lin, Yean-Kuen Fang, The Effect of Mobility Enhanced Technology on Device Characteristic and Reliability for sub-90nm SOI nMOSFETs, EDSSC Tainan, Taiwan, 2007.
  42. Jean-An Wang, Jiun-Yu Chen, Chia-Wei Hsu, Wen-Kuan Yeh, The Impact of Strain Technology on Device Performance and Reliability for sub-90nm SOI nMOSFETs , IEEE Proceedings of IEDMS, HsinChu, Taiwan, 2007.
  43. Yen-Chin Chen, Wen-Kuan Yeh, Ruey-Lue Wang, Hsuan-Der Yen,”2~10GHz UWB Low Noise Amplifier Using a Cascode Structure with Resistive Shunt Feedback”, Asia Pacific Microwave Conference, Bangkok, Thailand 2007.
  44. S M Wu, E Jahja, J W Wang, Wen-Kuan Yeh, “Study of Discrete Capacitor Embedded Process and Characterization Analysis in Organic-Base Substrate”, Electronic Packaging Technology Conference, December, Singapore, 2007.
  45. Sung-Mao Wu, E. Jahja, J. W. Wang, Z. Z. Lai, and ,Wen-Kuan Yeh, , “Embedded Process and Characterization Analysis o discrete capacitor in Organic-Base substrate”, Solid-State Device and Materials, September, Tsukuba, Japan, 2007.
  46. Wen-Kuan Yeh, Chieh-Ming Lai, Chien-Ting Lin, Yean-Kuen Fang, Chia-Wei Hsu, Chien-Ting Lin, “Extra Bonus on transistor Optimization with Stress Enhanced Notch-Gate Technology for sub-90 nm CMOSFET”, Solid-State Device and Materials, September, Tsukuba, Japan, 2007.
  47. Chia-Wei Hsu*, Sung-Mao Wu, Wen-Kuan Yeh, and Mark Li “Efficient Modeling of Packaging for Silicon-Base Inductor and MIM Capacitor”, ISSSE, Qubec, Canada, 2007.
  48. Wen-Kuan Yeh, Chieh-Ming Lai, Chien-Ting Lin, Yean-Kuen Fang “The Impact of Mobility Enhanced Technology on Device Performance and Reliability for sub-90nm SOI nMOSFETs, Proceedings of INFOS, Athen, Greece, 2007.
  49. Jia-Wei Syu, Wen-Kuan Yeh, “Efficient Extracting of Packaging Silicon-Base Inductor” IEEE Proceedings of IEDMS, Taiwan, 2006.
  50. Chieh-Ming Lai, Wen-Kuan Yeh, Chien-Ting Lin, Yean-Kuen Fang “Device Mobility Enhancement for 65nm FUSI CMOSFETs using a Second CESL Process ” IEEE Proceedings of IEDMS, Taiwan, 2006.
  51. C. T. Lin, Y. K. Fang, C. M. Lai, W. K. Yeh, C. H. Hsu, L. W. Chen, Mike Ma ”Device Optimization for sub-90nm CMOSFETs” IEEE Proceedings of IEDMS, Taiwan, 2006.
  52. Sheng Hsiung Chen, Wen-Kuan Yeh, “The Effect of Stressing History in Reliability Characteristics “IEEE Proceedings of EPTC, Singapore, 2006.
  53. (invited paper) Wen-Kuan Yeh, Chieh-Ming Lai, Chien-Ting Lin, Yean-Kuen Fang, “The impact of Stress Enhanced Technology for sub-90nm SOI MOSFETs, International Conference on Solid-State and Integrated-Circuit Technology”, October, 2006, Shanghai, China.
  54. S. H. Chen, S. L. Chen and W. K. Yeh, “A Study of Relationship of Wafer Breakage VS. Wafer Edge Analysis”, Solid-State Device and Materials, September, YoKohama, Japan, 2006.
  55. M. C. Tang, Y. K. Fang, W. K. Yeh and R. L. Wang, “Impacts of Layout Dimensions and Ambient Temperatures on Silicon Based On-Chip RF Interconnects”, Solid-State Device and Materials, September, YoKohama, Japan, 2006.
  56. C. M. Lai, Y. K. Fang, C. T. Lin, W. K. Yeh, C. W. Hsu, C. H. Hsu, L. W. Chen and M. Ma, “An Efficient Mobility Enhancement Engineering on 65nm FUSI CMOSFETs using a Second CESL Process”, Solid-State Device and Materials, September, YoKohama, Japan, 2006.
  57. C. T. Lin, Y. K. Fang, C. M. Lai, W. K. Yeh, C. W. Hsu, C. H. Hsu, L. W. Chen and M. Ma, “Efficient Improvement on Device Performance for sub-90nm SOI CMOSFETS”, Solid-State Device and Materials, September, YoKohama, Japan, 2006.
  58. H. Y. Kung, S. H. Chen, Y. S. Lai, E. Jahja, and W. K. Yeh, “The Reliability Characteristics of Wafer-Level Chip Scale Package under Various Current stressing”, Solid-State Device and Materials, September, YoKohama, Japan, 2006.
  59. Sheng Hsiung Chen, Wen-Kuan Yeh, “A New concept for Particle removes in Wet Bench Cleaning” IEEE Proceedings of IPFA, Singapore, 2006.
  60. Sheng Hsiung Chen, Wen-Kuan Yeh, “Ting Pitt are the Major Yield Killer caused by Metal Contamination in Wet Bench cleaning ” IEEE Proceedings of IPFA, Singapore, 2006.
  61. Chieh-Ming Lai, Yean-Kuen Fang, Wen-Kuan Yeh, Chien-Ting Lin, “The Impact of Strained Engineering for 65nm FUSI CMOSFETs” IEEE Proceedings of Device Research Conference, Penn State, 2006.
  62. Cheng-Han Chiang, Wen-Kuan Yeh, Shun-Peng Shih, “CMOS Low Noise Amplifier Design for 3-5GHz UWB System Application”, International Academic Conference, Taiwan 2006, P. 8.
  63. (invited paper) W.-K. Yeh, C.-M. Lai, Y.-K. Fang, C.-T. Lin, H.-H. Hu, K.-M. Chen, G.-W. Huang, “The impact of mobility modulation technology on device performance and reliability for sub-90nm SOI MOSFETs”, Electron Device and Solid-State Circuit, December, Hong-Kong, China, 2005.
  64. Chieh-Ming Lai, Chien-Ting Lin, Wen-Kuan Yeh, Yean-Kuen Fang, “Mobility Modulation Technology Impact on Device Performance and Reliability for <100> sub-90nm SOI CMOSFETs” IEEE Proceedings of EDMS, Taiwan, 2005,A-17;註:本篇已經獲得此大會傑出論文獎。
  65. Jia-Wei Syu, Wen-Kuan Yeh, Chien-Ting Lin, Chieh-Ming Lai, Yean-Kuen Fang, “The Impact of Body-Potential on Hot-Carrier-Induced Device Degradation for 90nm Partially-Depleted SOI nMOSFETs” IEEE Proceedings of EDMS, Taiwan, 2005, A-20
  66. C. T. lin, Y.K. Fang, and W. K. Yeh, “Interaction of STI with Various Mobility Enhancement Approaches”, Solid-State Device and Materials, September, Kobe, Japan, 2005.
  67. Mao-Chyuan Tang, Yean-Kuen Fang,Chieh-Ming Lai, Wen-Kuan Yeh, and Ta-Hsun Yeh, “Systematic Analysis and Modeling of On-Chip Spiral Inductors for CMOS RFIC Application, Solid-State Device and Materials, September, Kobe, Japan, 2005.
  68. Wen-Kuan Yeh, Chieh-Ming Lai, Chien-Ting Lin, and Yean-Kuen Fang, W. T. Shiau, “StressTechnology Impact on Device Performance and Reliability for <100> sub-90nm SOI CMOSFETs” , SOI Conference, October, USA, 2005.
  69. Da-Quan Huang, Wen-Kuan Yeh, Mao-Chung Chang, VLSI symposium, June, Kyoto, Japan, 2005.
  70. C. M. Lai, Y. K. Fang, W. K. Yeh, C. C. Hu, J. C. Lin and S. T. Pan, “Efficient Improvement of Hot-Carrier-Induced Degradation for Sub-0.1um CMOSFET”, IEEE Proceedings of 11th IPFA Taiwan, 2004, pp.275-278
  71. Chieh-Ming Lai, Yean-Kuen Fang, Wen-Kuan Yeh, “Channel width dependency of Hot-Carrier-induced Degradation for90nm Partially Depleted SOI Device” IEEE Proceedings of IEDMS, Taiwan, 2004, A.P.14
  72. Wen-Kuan Yeh, Chia-Che Hu, Chieh-Ming Lai, Shing-Tai Pan, Chao-Ching Ku and Yean-Kuan Fang “The Impact of Pad Test-Fixture for De-embedding on Radio-Frequency MOSFETs”, Solid-State Device and Materials, September, Tokyo, Japan, 2004.
  73. Chieh-Ming Lai, Yean-Kuen Fang, Wen-Kuan Yeh, Shing-Tai Pan, “Width Effect on Hot-Carrier-Induced Degradation for 90 nm Partially Depleted SOI CMOSFET”, Solid-State Device and Materials, September, Tokyo, Japan, 2004.
  74. Chieh-Ming Lai, Chia-Che Hu, Jung-Chun Lin, Shing-Tai Pan, Wen-Kuan Yeh, “Efficient Improvement of Hot-Carrier-Induced Degradation for Sub-0.1um CMOSFET”, Solid-State Device and Materials, September, Tokyo, Japan, 2004.
  75. Kun-Ming Chen, Wen-Kuan Yeh, Guo-Wei Huang, Yean—Kuen Fang, and Fu-Liang Yang, “Characterization and Modeling of SOI Varactors at Various Temperatures,” The 15th International Conference on Microelectronics, Cairo, Egypt, Dec. 9-11, 2003.
  76. Wen-Kuan Yeh, Shuo-Mao Chen*, Chieh-Ming Lai*, Yean-Kuen Fang*, “Efficient Suppression of Substrate Noise Coupling in CMOS Technology”, Solid-State Device and Materials, September, Tokyo, Japan, 2003.
  77. Chieh-Ming Lai, Chia-Che Hu, Jung-Chun Lin, Shing-Tai Pan, Wen-Kuan Yeh, “Efficient Improvement of Hot-Carrier-Induced Degradation for Sub-0.1um CMOSFET”, Solid-State Device and Materials, September, Tokyo, Japan, 2003.
  78. K.M. Chen, H.H. Hu, G.W. Huang, S.Y. Huang, A.S. Peng, Wen-Kuan Yeh, and C.Y. Chang, “Low-Frequency Noise in Partially-Depleted SOI MOSFETs Operating from Linear Region to Saturation Region at Various Temperatures,” 2003 International Conference on Solid State Devices and Materials, Tokyo, Japan, September 16-18, 2003, pp. 634-635.
  79. Wen-Kuan Yeh, Wen-Hang Wang, Yean-Kuen Fang, and Fu-Liang Yang, “Hot-Carrier-induced Degradation on 0.1um Partially Depleted SOI CMOSFET, IEEE IEDMS, December, Taipei, Taiwan, Dec, 2002.
  80. Shuo-Mao Chen*, Wen-Kuan Yeh, Yean-Kuen Fang*, Chien-Hao Chen**, Jason Lin**, and Ta-Hsun Yeh**,” A Novel Design of Suspended RF Inductor for Substrate Coupling Reduction“ IEEE IEDMS, December, Taipei, Taiwan, Dec, 2002.
  81. Wen-Kuan Yeh, Wen-Hang Wang, Yean-Kuen Fang, and Fu-Liang Yang, “Hot-Carrier-induced Degradation on 0.1um Partially Depleted SOI CMOSFET, SOI Conference, October, Hawaii, USA, 2002.
  82. Wen-Kuan Yeh, Wen-Hang Wang, Yean-Kuen Fang, and Fu-Liang Yang, “Hot-Carrier-induced Degradation on 0.1um Partially Depleted SOI CMOSFET with thin Oxide”, Solid-State Device and Materials, September, Nagoya, Japan, 2002.
  83. Wen-Kuan Yeh and Jih-Wen Chou, “Thermal Effect of 0.1um Partially Depleted SOI CMOSFET”, Insulator Films on Semiconductor Meeting, June, Italy, 2001.
  84. Wen-Kuan Yeh and Cjiutsung Huang, “High Performance 0.1um Partially Depleted SOI CMOSFET, SOI Conference, October, USA, 2000.
  85. Wen-Kuan Yeh, Chih-Yung-Lin and Shin-Wei Sun, “The Impact of Gate Oxide Scaling (32A-12A) and power Supply for Sub-0.1um CMOSFETs”, Solid-State Device and Materials, October, Japan, 2000.
  86. Wen-Kuan Yeh, Jih-Wen Chou, and Shin-Wei Sun,"A Low Thermal-Budget high-performanced 0.25-0.18um merged logic and Dram ” Solid-State Device and Materials, October, Japan, 1999.
  87. M.H. Tsai, R. Augurlv, V. Blachkel, R. H. Havemann, E. T. Ogawa, P. S. Ho, W. K. Yeh, S. L. Shue, C. H. Yu, and M. S. Liang' Electromigration Reliability of Dual Damascene Cu/CVD SiOC Interconnects”, Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International, 4-6 June 2001 Page(s):266 - 268; Digital Object Identifier 10.1109/IITC.2001
  88. Wen-Kuan Yeh, Jih-Wen Chou, and Shin-Wei Sun,"A Novel Shallow Trench Isolation with Mini-Spacer Technology” Solid-State Device Meeting, p98, 1998.
  89. Tony Lin, Coming Chen, Wen-Kuan Yeh , Jih-Wen Chou,and Shin-Wei Sun, “A Fully Planarized 6-Level-Metal CMOS Technology for 0.25-0.18 Micron Foundry Manufacturing”, IEEE International Electron Devices Meeting, p851, USA, 1997.
  90. Wen-Kuan Yeh and Mao-Chieh Chen, “Barrier Property of TaN and WN with RTN against Copper and Al”, p.541, VMIC, USA, 1996.
  91. Wen-Kuan Yeh, Mao-Chieh Chen, and Mao-Shiung Lin,"An Efficient Improvement on Thermal Stability of W-filled Contact" Solid State Device and Materials, Japan, 1995.
  92. Wen-Kuan Yeh, Mao-Chieh Chen, and Mao-Shiung Lin, “Deposition properties of selective W-CVD “, ICEM, 1994.

專利論文
  1. 葉文冠,”金屬沉積技術與設備” 電子月刊,7月號,第12期, pp.58~P.69, (1996).
  2. 葉文冠, ”矽絕緣層(Silicon-on-isolation)元件技術的現況與挑戰” 電子月刊,10月號, 87期, pp. 193-207, (2002).
  3. 葉文冠, ”絕緣層上矽可變電容的溫度特性分析及模型化技術”奈米通訊,12卷, 2期, pp. 1-6, (2004).
  4. 葉文冠, ”High-K/Metal Gate 於奈米電晶體之特性應用” 電子月刊,9月號, 170期, pp. 1917-127, (2009).

專利
(A)發明專利(B)新型專利。
類別 專利名稱 國別 專利號碼 發明人 專利權人 專利期間
B 選擇性化學汽相鎢塞沉積之前置處理方法 中華民國 084839 葉文冠 國科會 1997/1/21 ~ 2015/6/5
B 選擇性化學汽相鎢塞沉積之前置處理法 中華民國 5670016 葉文冠 國科會 1997/9/23 ~ 2015/11/15
A 改善熱載子造成半導體元件退化之製程 中華民國 090043 葉文冠 聯華電子 1997/10/1 ~ 2016/10/18
A 金屬閘電極製程 中華民國 091187 葉文冠 聯華電子 1997/11/21 ~ 2016/11/17
A 形成金氧半元件中淡雜汲極的製造方法 中華民國 088972 葉文冠 聯華電子 1997/8/11 ~ 2017/3/16
A 金氧半場效電晶體元件之製造方法 中華民國 092407 葉文冠 聯華電子 1998/1/21 ~ 2018/9/18
A 阻礙層的形成方法 中華民國 102568 葉文冠 聯華電子 1999/4/21 ~ 2017/12/18
A 電容製造方法 中華民國 102882 葉文冠 聯華電子 1999/5/1 ~ 2017/12/21
A 形成金氧半導體元件之方法 中華民國 103297 葉文冠 聯華電子 1999/5/21 ~ 2017/4/7
A 雙重嵌金法 中華民國 104012 葉文冠 聯華電子 1999/6/11 ~ 2017/12/18
A 金氧半場效電晶體元件之製造方法 中華民國 105322 葉文冠 聯華電子 1999/6/21 ~ 2017/12/21
A 閘極的製造方法 中華民國 090043 葉文冠 聯華電子 1999/7/21 ~ 2017/10/17
A 淺溝渠隔離法 中華民國 110997 葉文冠 聯華電子 2000/1/11 ~ 2018/4/26
A 半導體元件的結構與製造方法 中華民國 111469 葉文冠 聯華電子 2000/1/21 ~ 2018/9/10
A 閘極的製造方法 中華民國 111473 葉文冠 聯華電子 2000/2/11 ~ 2018/9/18
A 半導體元件之製造方法 中華民國 111486 葉文冠 聯華電子 2000/1/21 ~ 2018/10/20
A 互補式金氧半場效電晶體元件之製造方法 中華民國 112258 葉文冠 聯華電子 2000/2/21 ~ 2018/4/21
A 製造淺溝渠隔離結構的方法 中華民國 112482 葉文冠 聯華電子 2000/3/1 ~ 2017/10/19
A 簡化嵌入式動態隨機存取記憶體製程之製造方法 中華民國 112583 葉文冠 聯華電子 2000/3/1 ~ 2018/8/20
A 嵌入式動態隨機存取記憶體製程之製造方法 中華民國 113777 葉文冠 聯華電子 2000/4/11 ~ 2018/9/13
A 改善半導體元件插排效應之製造方法 中華民國 114706 葉文冠 聯華電子 2000/5/21 ~ 2018/9/2
A 金氧半元件製造方法 中華民國 115616 葉文冠 聯華電子 2000/6/1 ~ 2018/9/13
A 半導體元件之製造方法及其結構 中華民國 115780 葉文冠 聯華電子 2000/6/1 ~ 2018/2/9
A 金氧半導體之製造方法 中華民國 115857 葉文冠 聯華電子 2000/6/1 ~ 2018/9/4
A 金氧半電晶體之製造方法 中華民國 115860 葉文冠 聯華電子 2000/6/1 ~ 2018/9/7
A 金屬介層窗之製造方法 中華民國 118319 葉文冠 聯華電子 2000/7/21 ~ 2018/4/19
A 快閃記憶體的製造方法 中華民國 119984 葉文冠 聯華電子 2000/9/1 ~ 2019/3/18
A 使用低介電常數物質之雙鑲嵌製程 中華民國 131244 葉文冠 聯華電子 2001/4/21 ~ 2019/6/3
A 金氧半元件的製造方法 中華民國 123967 葉文冠 聯華電子 2001/4/21 ~ 2019/6/3
A 銅銲墊的製造方法 中華民國 129261 葉文冠 聯華電子 2001/3/21 ~ 2019/7/5
A 降低源極/汲極區結合電容之方法 中華民國 130925 葉文冠 聯華電子 2001/4/21 ~ 2018/9/2
A 結合邏輯電路合電容的方法 中華民國 134036 葉文冠 聯華電子 2001/5/16 ~ 2019/9/6
A 具有選擇性磊晶成長層之半導體元件 中華民國 133303 葉文冠 聯華電子 2001/4/21 ~ 2019/6/3
A 雙鑲嵌製程 中華民國 132925 葉文冠 聯華電子 2001/5/16 ~ 2019/6/13
A 積體電路之銅保險絲結構 中華民國 135142 葉文冠 聯華電子 2001/6/7 ~ 2020/1/2
A 具有抗穿透摻雜通道之場效電晶體的製造方法 中華民國 134268 葉文冠 聯華電子 2001/6/7 ~ 2018/10/7
A 以雙鑲嵌法形成金屬內連線的方法 中華民國 134500 葉文冠 聯華電子 2001/6/7 ~ 2019/11/8
A 具有共同接觸插塞之小尺寸半導體元件 中華民國 146031 葉文冠 聯華電子 2001/12/1 ~ 2019/1/7
A 金屬接觸窗之結構與形成方法觸窗開口的製造方法 中華民國 147801 葉文冠 聯華電子 2001/12/21 ~ 2018/4/26
A 一種雙嵌入式同接觸插塞 中華民國 150455 葉文冠 聯華電子 2002/01/11 ~ 2021/2/2
A 自動對準接觸窗開口的製造方法 中華民國 154879 葉文冠 聯華電子 2002/05/01 ~ 2019/3/2
A 抑制短通道效應之深次微米場效電晶體之製造方法 中華民國 154828 葉文冠 聯華電子 2002/07/01 ~ 2020/11/1
B The pretreatment of selective W-CVD USA 5760016 WKYEH NSC 1997/9/23 ~ 2015/11/15
A Method of Manufacturing Complementary Metallic-oxide-Semiconductor USA 6083783 WKYEH UMC 1998/6/9~
A Method of Forming of Metallic Oxide Capacitor USA 5786255 WKYEH UMC 1998/7/28~
A Metallic Oxide Semiconductor(MOS)Device with reduced Level of Degradation Caused By Hot Carrier Degradation USA 5861329 WKYEH UMC 1999/1/19~
A Method for Improving Hot Carrier Degradation USA 5920782 WKYEH UMC 1999/7/6~
A Process of Fabricating Metal Gate Electrode USA 5946598 WKYEH UMC 1999/8/31~
A Manufacture of MOSFET having LDD S/D region USA 6000852 WKYEH UMC 1999/2/21~
A Metallic Oxide Semiconductor Field Effect Transistor Device Fabrication Process USA 6228100 WKYEH UMC 1999/12/28
A Method of Forming A Barrier Layer USA 6008118 WKYEH UMC 1999/12/28~
A Method of Fabricating Semiconductor Device with a Gate Side Air Gap Structure USA 6015746 WKYEH UMC 2000/1/18~
A Method of Forming of Metallic Oxide Semiconductor Transistor USA 6022785 WKYEH UMC 2000/2/8~
A Shallow Trench Isolation Technique Implantation Method USA 6048771 WKYEH UMC 2000/4/11~
A Method of Forming A Capacitor Utilizing an Ion Implantation Method USA 6057189 WKYEH UMC 2000/5/2~
A Gate Structure of a Semiconductor Device having an Air Gap USA 6064107 WKYEH UMC 2000/5/16~
A Method For Fabrication Local Interconnect USA 6083827 WKYEH UMC 2000/7/4~
A Semiconductor Device with Shared Contact USA 6100569 WKYEH UMC 2000/8/8~
A Method of manufacturing MOS device Using Anti Reflective coating USA 6117743 WKYEH UMC 2000/9/12~
A STI Process for eliminating Kink effect USA 6153478 WKYEH UMC 2000/10/28~
A Method for manufacturing MOS USA 6153483 WKYEH UMC 2000/11/28~
A Method for formatting a Transistor with Selective epitaxial Growth Film USA 6165857 WKYEH UMC 2000/12/26~
A Method for fabricating a metal oxide Semiconductor transistor USA 6022789 WKYEH UMC 2001/2/8~
A Method for fabrication a metal oxide semiconductor device USA 6177336 WKYEH UMC 2001/1/23~
A Method for manufacturing gate terminal with Anti Reflective coating USA 6197642 WKYEH UMC 2001/3/6~
A Method for fabricating a metal oxide semiconductor transistor USA 6211023 WKYEH UMC 2001/4/3~
A Dual damascence process using low-dielectric constant material USA 6114233 WKYEH UMC 2001/9/5~
A Method for formatting a metal-oxide-semiconductor transistor USA 6277699 WKYEH UMC 2001/8/21~
A Method for suppressing junction capacitance of source/drain regions USA 6274448 WKYEH UMC 2001/8/14~
A Method for combing logic circuit and capacitor USA 6281134 WKYEH UMC 2001/8/28~
A structure of combined passive elements and logic circuit on a silicon on insulator wafer USA 6294834 WKYEH UMC 2001/9/25~
A Self-aligned contact process USA 6306701 WKYEH UMC 2001/10/23~
A Electrostatic Discharge Protection Apparatus with Silicon Control Rectifier and the method of fabrication the same USA 6376882 WKYEH UMC 2002/04/23~
A Method for new interconnection fabrication Korea 0344250 WKYEH UMC 2002/07/20~
A Semiconductor device having varied dopant density regions USA 6451675 WKYEH UMC 2002/09/17~
A Copper fuse for integrated circuit USA 6455913 WKYEH UMC 2002/09/24~
A Electrostatic Discharge Protection Apparatus with Silicon Control Rectifier and the Method of Fabricating the same USA 6548360 WKYEH UMC 2003/04/15~
A Electrostatic Discharge Protection Apparatus with Silicon Control Rectifier and the Method of Fabricating the same JAPAN 3487407 WKYEH UMC 平成10年3月23日~